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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC4050 Hex high-to-low level shifter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Hex high-to-low level shifter FEATURES * Output capability: standard * ICC category: SSI GENERAL DESCRIPTION The 74HC4050 is a high-speed Si-gate CMOS device and is pin compatible with the "4050" of the "4000B" series. It is specified in compliance with JEDEC standard no. 7A. The 74HC4050 provides six non-inverting buffers with a modified input protection structure, which has no diode connected to VCC. Input voltages of up to 15 V may QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL / tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V (CL x VCC2 x fo) = sum of outputs ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay nA to nY input capacitance power dissipation capacitance per buffer note 1 CONDITIONS HC CL = 15 pF; VCC = 5 V 7 3.5 14 74HC4050 therefore be used. This feature enables the non-inverting buffers to be used as logic level translators, which will convert high level logic to low level logic, while operating from a low voltage power supply. For example 15 V logic ("4000B series") can be converted down to 2 V logic. The actual input switch level remains related to the VCC and is the same as mentioned in the family characteristics. APPLICATIONS * Converting 15 V logic ("4000B" series) down to 2 V logic. UNIT ns pF pF December 1990 2 Philips Semiconductors Product specification Hex high-to-low level shifter PIN DESCRIPTION PIN NO. 1 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 8 13, 16 VCC 1Y to 6Y 1A to 6A GND n.c. SYMBOL data outputs data inputs ground (0 V) not connected NAME AND FUNCTION positive supply voltage 74HC4050 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Hex high-to-low level shifter 74HC4050 Fig.5 Fig.4 Functional diagram. Input protection for HC4050. Single sided thick oxide field effect metal gate transistor as input protection. Fig.6 Logic diagram (one level shifter). FUNCTION TABLE (1) INPUT nA L H Note 1. H = HIGH voltage level L = LOW voltage level OUTPUT nY L H December 1990 4 Philips Semiconductors Product specification Hex high-to-low level shifter RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL VCC VIK -IIK IOK IO ICC; IGND Tstg PARAMETER DC supply voltage DC input voltage range DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with: - standard outputs storage temperature range power dissipation per package Ptot plastic DIL plastic mini-pack (SO) RECOMMENDED OPERATING CONDITIONS 74HC SYMBOL VCC VI Tamb Tamb PARAMETER min. DC supply voltage DC input voltage range 2.0 GND - typ. 5.0 max. 6.0 15 +85 +125 1000 500 400 650 1000 V V C C UNIT 750 500 mW mW -65 MIN. -0.5 -0.5 MAX. +7 +16 20 20 25 UNIT V V mA mA mA for VI < -0.5 V 74HC4050 CONDITIONS for VO < -0.5 V or VO > VCC + 0.5 V for -0.5 V < VO < VCC + 0.5 V 50 +150 mA C for temperature range: -40 to +125 C 74HC above +70 C: derate linearly with 12 mW/K above +70 C: derate linearly with 8 mW/K CONDITIONS operating ambient temperature range -40 operating ambient temperature range -40 see DC and AC characteristics VCC = 2.0 V; VIN = 2.0 V VCC = 4.5 V; VIN = 4.5 V VCC = 6.0 V; VIN = 6.0 V VCC = 6.0 V; VIN = 10.0 V VCC = 6.0 V; VIN = 15.0 V tr, tf input rise and fall times 6.0 ns December 1990 5 Philips Semiconductors Product specification Hex high-to-low level shifter DC CHARACTERISTICS FOR 74HC Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 UNIT V CC (V) 74HC4050 TEST CONDITIONS VI OTHER min. typ. max. min. max. min. VIH HIGH level input voltage LOW level input voltage HIGH level output voltage - all outputs HIGH level output voltage - standard outputs LOW level output voltage - all outputs LOW level output voltage - standard outputs input leakage current 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 1.5 1.3 3.15 2.4 4.2 3.1 0.7 1.8 2.3 2.0 4.5 6.0 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 1.5 3.15 4.2 VIL 0.5 1.35 1.8 V VOH V VIH or VIL VIH or VIL VIH or VIL VIH or VIL VCC or GND 15 V -IO = 20 A -IO = 20 A -IO = 20 A -IO = 4.0 mA -IO = 5.2 mA IO = 20 A IO = 20 A IO = 20 A IO = 4.0 mA IO = 5.2 mA VOH V VOL 0.1 0.1 0.1 0.4 0.4 1.0 V VOL V II A 6.0 0.5 5.0 5.0 A 2.0 to 6.0 6.0 ICC quiescent supply current 2.0 20.0 40.0 A 15 V or GND December 1990 6 Philips Semiconductors Product specification Hex high-to-low level shifter AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay nA to nY output transition time 25 9 7 19 7 6 max. 85 17 14 75 15 13 -40 to +85 min. max. 105 21 18 95 19 16 -40 to +125 min. max. 130 26 22 110 22 19 ns 2.0 4.5 6.0 2.0 4.5 6.0 UNIT 74HC4050 TEST CONDITIONS VCC WAVEFORMS (V) Fig.7 tTHL/ tTLH ns Fig.7 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7 |
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